Shallow trench isolation (STI) and deep trench isolation (DTI) are known for electrically isolating neighboring devices such transistors from one another. STI is generally 0.2 μm to 2 μm deep, while DTI is generally from 2 μm to 40 μm deep. The typical STI or DTI formation process includes growing a blanket pad oxide layer, depositing a blanket silicon nitride layer (with an optional top deposited silicon oxide layer) followed by a trench mask, then a reactive ion etch (RIE) through the silicon nitride and pad oxide and into the typical crystalline silicon substrate surface underneath to form trenches. Some trench processes then add an angled implant into the silicon at the trench sidewalls for increasing the oxidation rate or for an isolation enhancement (e.g., providing a low resistance connection to a same doped type buried layer to form an isolation tank). The trench implant is usually a high dose ion implant, typically using an implant dose of at least about 1×1015 cm−2.
Suitable trench sidewall implant species include argon or other inert elements, oxygen, and active silicon dopant elements such as phosphorous and arsenic for an isolation enhancement. There can be some oxidation performed before this sidewall trench implant, such as a growing a silicon oxide layer for example. Following the angled trench implant a rapid thermal processing (RTP) or a furnace anneal may be used to anneal out some of the implant-induced crystal damage from the trench implant.
The trench mask is then stripped and a thermal liner oxide layer is grown (e.g., such as 1050° C.) to form an oxide lined trench which can also provide some annealing if it is a significant thermal cycle performed prior to any significant oxidation taking place. Next, a deposited oxide layer such as a high density plasma (HDP) oxide layer or a polysilicon layer is deposited to fill the oxide lined trench and the substrate is again heated in the case of a deposited oxide to densify the deposited oxide. In the case of polysilicon fill, the polysilicon may be doped, typically in-situ doped. Finally, the silicon oxide or polysilicon overburden is polished back to the buried silicon nitride surface generally using Chemical Mechanical Polishing (CMP), and then the silicon nitride/pad oxide is then stripped off.